Semiconductor memory device with self correction circuit

Details Semiconductor memory device with self correction circuit Semiconductor memory device with self correction circuit

1984-04-03

1986-09-30

Atkinson, Charles E.

Excavating

371 21, G06F 1100, G11C 2900

Patent

active

046150307

ABSTRACT:
A semiconductor memory chip (FIG. 2) with a memory array (3) is backed-up by a self diagnosis circuit (15, 16, 17, 18, 19) so that an error of a single defective cell, or a single defective row of cells, or a single defective column of cells is automatically corrected. The backup circuit comprises a self diagnosis circuit (15) which has a one-bit memory for storing information in write phase before it is stored in a cell of the memory array (3), and comparison means for comparing the content of said one-bit memory with information immediately read out of the same cell in said write phase, a register means (16, 17) for storing the address of the memory array when said self diagnosis circuit (15) provides an error signal (P) according to the result of the comparison, and an inverter circuit (19) for inverting the output of the addressed memory cell when selected address in read phase coincides with the content of said register means (16,17). Thus, an error of a cell of the memory array is automatically corrected. Said self diagnosis circuit is mounted on the same semiconductor chip as that of a memory array itself.

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Quinn et al., Dynamic Testing of Memory Arrays Which Utilize ECC Logic, Electronic Engineering, vol. 53, No. 650, Mar. 1981, pp. 33-36, 38, 40-43.
Williams, High-Speed, Low-Volume Data Array Self-Test, IBM Technical Disclosure Bulletin, vol. 23, No. 8, Jan. 1981, pp. 3596-3597.

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