Data processing system with interrupt facilities

Details Data processing system with interrupt facilities Data processing system with interrupt facilities

1982-10-28

1986-09-30

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 900

Patent

active

046150196

ABSTRACT:
The system comprises a series of input-output units (I/O) connected by means of a bus (21) to a central unit (CPU) capable of accepting at least one category of vectored interrupts requested by the I/O units and a category of non-vectored interrupts.
The vectored interrupts are divided into at least two levels in which relative priority between units belonging to the same level depends on the position of the respective connection to a conductor of the bus.
Performance of an interrupt is carried out by means of a routine which includes a closing tail. The performance of a series of interrupts of the same level may be carried out serially by suppressing the tail of all the routines except the last.
The non-vectored interrupts are divided into a plurality of levels which are defined by the content of a register which is capable of being variably loaded by means of a suitable instruction. The content of the register in turn addresses a specific routine for performance of the interrupt.
The I/O unit may also be connected for direct access to a common memory (RAM) with a priority defined by the position of the respective connection to another conductor of the bus.

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patent: 4414624 (1983-11-01), Summer, Jr. et al.
patent: 4435780 (1984-03-01), Herrington et al.

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