Method for producing a three-dimensional semiconductor device

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437 89, 437 90, 437106, 437915, 437 57, 148DIG164, H01L 2904, H01L 2120

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054223024

ABSTRACT:
A semiconductor device has an insulated gate type transistor. The insulated gate type transistor is formed on an insulating surface of substrate.
The insulated gate type transistor is formed in a single crystal layer which is grown from a single nucleus formed on nucleation region which is provided on said insulating surface, which has sufficiently greater nucleation density than material of said insulating surface and which has sufficiently small size so that only one nucleus can be grown.

REFERENCES:
patent: 3403439 (1968-10-01), Bailey
patent: 3549432 (1970-12-01), Sivertsen
patent: 3620833 (1971-11-01), Gleim et al.
patent: 3900943 (1975-08-01), Sirtl
patent: 4131496 (1978-12-01), Weitzel et al.
patent: 4174422 (1979-11-01), Mathews et al.
patent: 4279688 (1981-07-01), Abrahams et al.
patent: 4443488 (1984-04-01), Little et al.
patent: 4489478 (1984-12-01), Sakurai
patent: 4498226 (1985-02-01), Inoue et al.
patent: 4507158 (1985-03-01), Kamins et al.
patent: 4522662 (1985-06-01), Bradbury et al.
patent: 4569700 (1986-02-01), Toyama
patent: 4578142 (1986-03-01), Corboy, Jr. et al.
patent: 4592792 (1986-06-01), Corby, Jr. et al.
patent: 4637127 (1987-01-01), Kurogi et al.
patent: 4685199 (1987-08-01), Jastrzebski
patent: 4749441 (1988-06-01), Christenson et al.
patent: 5008206 (1991-04-01), Shinohara et al.
patent: 5010033 (1991-04-01), Tokunaga et al.
patent: 5013670 (1991-05-01), Arikawa et al.
patent: 5155058 (1992-10-01), Fujiwara et al.
Claassen et al., "The Nucleation of CVD Silicon on SiO.sub.2 and Si.sub.3 N.sub.4 Substrates", J. Electrochem. Soc., vol. 127, No. 1, Jan. 1980, pp. 194-202.
Brice, Crystal Growth Processes, (John Wiley and Sons), Blackie and Son, Ltd., 1986, p. 75.
Jastrezebski, "SOI by CVD: Epitaxial Lateral Overgrowth (ELO) Process--A Review", J. of Crystal Growth, vol. 63, 1983, pp. 493-526.
Ohkura et al., "Orientation Controlled SOI by Line-Shaped Laser-Beam Seeded Lateral Epitaxy for CMOS Stacking", Japanese Journal of Applied Physics, 17th Conf. on Solid State Devices and Materials, Aug. 1985, pp. 143-146.
Blaem et al., "Nucleation and Growth of Silicon Films by Chemical Vapour Deposition", Philips Technical Review, vol. 41, No. 2, pp. 60-69 (1983-84).

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