Fishing – trapping – and vermin destroying
Patent
1994-02-28
1995-06-06
Thomas, Tom
Fishing, trapping, and vermin destroying
437 59, 437162, 437200, 148DIG9, H01L 21265
Patent
active
054222907
ABSTRACT:
In a BiCMOS process, a gate oxide is grown over the MOS transistors and over the base regions of the bipolar transistors. The base is implanted through the gate oxide and, in some embodiments, through a thin polysilicon layer overlying the base oxide. Then an opening is etched over the base regions in the thin polysilicon layer and the gate oxide, another polysilicon layer is deposited, and the two polysilicon layers are patterned to provide emitter contact regions and gate regions. The polysilicon etch terminates on the gate oxide. After an LDD implant or implants, an insulating layer is deposited and etched anisotropically to create spacers on the sidewalls of the emitter contact regions and the gate regions. During the etch, the gate oxide is etched away around the spacers to expose the extrinsic base regions and the source and drain regions. Because both the extrinsic base regions around the spacers and the source and drain regions around the spacers are covered only by the insulating layer and the gate oxide, and because each of the insulating layer and the gate oxide has a uniform thickness over the base, source and drain regions, the overetch required is identical over the bipolar MOS transistors. Other features and embodiments are described in the specification, the drawings and the claims.
REFERENCES:
patent: 4570328 (1986-02-01), Price et al.
patent: 4897709 (1990-01-01), Yokoyama et al.
patent: 4931411 (1990-06-01), Tigelaar et al.
patent: 4933295 (1990-06-01), Feist
patent: 4960726 (1990-10-01), Lechaton et al.
patent: 4980020 (1990-12-01), Douglas
patent: 5045493 (1991-09-01), Kameyama et al.
patent: 5059549 (1991-10-01), Furuhata
patent: 5094980 (1992-03-01), Shepela
patent: 5098854 (1992-03-01), Kapoor et al.
patent: 5102811 (1992-04-01), Scott
patent: 5124271 (1992-06-01), Havemann
patent: 5164331 (1992-11-01), Lin et al.
patent: 5171702 (1992-12-01), Prengle et al.
patent: 5175118 (1992-12-01), Yoneda
patent: 5179031 (1993-01-01), Brassington et al.
patent: 5218224 (1993-06-01), Taguchi
patent: 5219784 (1993-06-01), Solheim
patent: 5274267 (1993-12-01), Moksvold
patent: 5324672 (1994-06-01), Anmo et al.
patent: 5334549 (1994-08-01), Eklund
U.S. patent application Ser. No. 08/085,436 filed by M. J. Grubisich on Jun. 30, 1993 entitled: "Transistors and Methods for Fabrication Thereof".
Iranmanesh et al., "A 0.8-.mu.m Advanced Single-Poly BiCMOS Technology for High-Density and High-Performacnce Applications," IEEE Journal of Solid State Circuits, vol. 26, No. 3, Mar., 1991, pp. 422-426.
J. L. de Jong et al., "Single Polysilicon Layer Advanced Super High-speed BiCMOS Technology," Paper 7.4, IEEE, 1989, pp. 182-185.
A. Nouailhat et al., "Development of Advanced CMOS-Compatible Bipolar Transistor for BiCMOS Technology," Electronics Letters, vol. 24, No. 25, Dec. 8. 1988, pp. 1581-1983.
Stanley Wolf, "Silicon Processing for the VLSI Era," vol. 2, Process Integration, Lattice Press, 1990, pp. 13-44, 143-150, 162-169, 482-483, 486-502, 504, 505, 510-522, 532-535, 538-543 and 546-551.
National Semiconductor Corporation
Nelson H. Donald
Nguyen Tuan
Robinson Stephen R.
Shenker Michael
LandOfFree
Method of fabricating BiCMOS structures does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating BiCMOS structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating BiCMOS structures will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-987290