Speech analysis circuits using an inverse lattice network

Details Speech analysis circuits using an inverse lattice network Speech analysis circuits using an inverse lattice network

1981-07-06

1984-04-17

Malzahn, David H.

Boots, shoes, and leggings

381 41, G06F 1531, G10L 100

Patent

active

044438591

ABSTRACT:
An adaptive filter suitable for speech analysis which is constructable on a silicon chip. The filter has a single multiplier and a single adder in series together with appropriate registers or memories so that the output of the adder is either looped back to the adder itself or alternatively is looped, after a delay, to the multiplier so as to perform the operations of an all-zero digital lattice filter in computing a moving average, employing linear predictive coding. Another register provides the multiplier with the constant values typically associated with lattice filter coefficients. Preferably the multiplier is an M-stage pipeline multiplier so as to reduce the area necessary for its incorporation on a silicon chip. The filter accepts digital samples of the voice input and outputs a compressed data representation of the input.

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patent: 4378469 (1983-03-01), Fette
Bayless et al., "Voice Signals: Bit-by-Bit", IEEE Spectrum, Oct. 1973, pp. 28-34.
Makhoul, "Linear Prediction: A Tutorial Review", Proceeding of the IEEE, vol. 63, Apr. 1975, pp. 561-580.
Wiggins, "Low Cost Voice Response Systems Based on Speech Synthesis", SAE Technical Paper Series No. 800192, Feb. 1980.

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