Patent
1976-03-31
1978-04-11
Jackmon, Edith S.
58 855, 328 48, G04C 300, G04B 2700
Patent
active
040831760
ABSTRACT:
A time correcting system for an electronic timepiece. The correcting system includes a single manually operable switch connected to a switching circuit for developing a chatter-free switching signal. A gate circuit is responsive to the switching signal for applying a time reference signal to time measuring circuitry of the timepiece. A counter is connected to receive a signal from a certain stage of a divider circuit of the timepiece for developing a count representative of the correcting mode of the correcting system. A resetting circuit resets all of the dividing stages of the dividing circuit when the counter develops a predetermined count and releases all of the divider stages from the reset state in response to opening of the manually operable switch. A first pulse generating circuit develops a pulse signal in response to termination of the switching signal before the counter develops a predetermined count in order to correct slow time. A flip-flop circuit set by the output signal of the first pulse generating circuit develops an output signal for enabling the divider circuit, and a second pulse generating circuit receives the output of the divider circuit for developing an output pulse to reset the flip-flop to disable the dividing circuit to correct fast time.
REFERENCES:
patent: 3817020 (1974-06-01), Esaki
patent: 3841081 (1974-10-01), Komaki
patent: 3852951 (1974-12-01), Sauthier
patent: 3889460 (1975-06-01), Yasukawa et al.
patent: 3948035 (1976-04-01), Kusumoto
patent: 3961472 (1976-06-01), Riehl
Adams Bruce L.
Burns Robert E.
Jackmon Edith S.
Kabushiki Kaisha Daini Seikosha
Lobato Emmanuel J.
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