Method for controlling DRAM memory in a microcomputer

Details Method for controlling DRAM memory in a microcomputer Method for controlling DRAM memory in a microcomputer

1993-12-13

1995-08-08

Elmore, Reba I.

Boots, shoes, and leggings

3642461, 36424691, 3649642, 3649649, 364968, 364DIG1, 365222, G06F 1208, G06F 1318

Patent

active

054407117

ABSTRACT:
There is provided a microcomputer including therein a DRAM controller, the DRAM controller including a refresh controller for refreshing a DRAM and an access controller for controlling the access to the DRAM whereby the need of a DRAM controlling external circuit that suffers from severe timing adjustment is eliminated and hence the DRAM is made directly connectable to the microcomputer.

REFERENCES:
patent: 4796232 (1989-01-01), House
patent: 4870622 (1989-09-01), Aria et al.
patent: 4884234 (1989-11-01), Keys et al.
patent: 4924381 (1990-05-01), Tikuume
patent: 4943960 (1990-07-01), Komatsu et al.
patent: 4954951 (1990-09-01), Hyatt
patent: 4965717 (1990-10-01), Cutts, Jr. et al.
patent: 5134699 (1992-07-01), Aria et al.
patent: 5317709 (1994-05-01), Sugimoto
Goodman, et al. "The Use of Static Column RAM as a Memory Hierarchy," Unknown IEEE publication, 1984.
Intel Advance Information 80C186, "CHMOS High Integration 16-BIT Microprocessor", Sep., 1987, Intel Corporation.
8203 64K Dynamic Ram Controller manual, Intel, Nov., 1987, pp. 2-1-2-16.

Affiliated with

Also associated with

Rating

Method for controlling DRAM memory in a microcomputer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for controlling DRAM memory in a microcomputer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for controlling DRAM memory in a microcomputer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-978240