Circuit for outputting a data signal following an output enable

Details Circuit for outputting a data signal following an output enable Circuit for outputting a data signal following an output enable

1991-07-17

1992-12-22

Pascal, Robert J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307473, H03K 1900

Patent

active

051736276

ABSTRACT:
The invention provides an output enable control circuit with a three gate delay. The circuit includes a CMOS passgate or other transmission control and filtering means, one or more shunting transistors, and an output driver. The CMOS passgate, in conjunction with a first shunting transistor, allows an output enable command to control transmission of the data signal to the output driver. By properly tuning the CMOS passgate, bounce on the power supply and ground lines can be minimized. A second shunting transistor can be included to allow other data control signals, such as a write enable or chip select signal, to cease data output by the circuit. Additionally, a third shunting transistor, controlled by the data signal, can be included to allow fast turn off of the output driver.

REFERENCES:
patent: 4703203 (1987-10-01), Gallup et al.
patent: 5025182 (1991-06-01), Farmer
Will C. H. Gubbels et al., "A 40-ns/100-pF Low-Poer Full-CMOS 256K (23Kx8) SRAM", IEEE Jour. of Solid-State Cir., vol. SC-22, No. 5, Oct. 1987, p. 741.
Thaddeus Gabra et al., "Ground Bounce Control inCMOS Integrated Circuits", IEEE International Solid-State Cir. Conf., p. 88, Feb. 1988.
Karl L. Wang et al., "A 21-ns 32Kx8 CMOS Static RAM with a Selectively Pumped p-well Array", IEEE Jour. of Solid-State Cir., vol. SC-22, No. 5, Oct. 1987, p. 704.
George Canepa et al., "A 90ns 4Mb CMOS EPROM", IEEE Int'n Solid-State Cir. Conf., p. 120, Feb. 1988.
Tomohisa Wada et al., "A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon", IEEE Journal of Solid-State Cir., vol. SC-22, No. 5, Oct. 1987, p. 727.

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