Titanium silicide local interconnect process

Details Titanium silicide local interconnect process Titanium silicide local interconnect process

1991-12-20

1992-12-22

Quach, T. N.

Fishing, trapping, and vermin destroying

437 52, 437190, 437193, 437 41, 148DIG19, H01L 21283

Patent

active

051734508

ABSTRACT:
A TiSi.sub.2 LI process solves the problems of poor junction integrity and rapid dopant outdiffusion by adding a second titanium deposition on the amorphous silicon/titanium stack and reducing the initial titanium thickness to its minimum required value for amorphous silicon etch stop. Referring to FIG. 5 of the drawings, titanium layer 60 reacts at exterior surface 58 of sidewall oxide 59 to form TiN layer 57. Layer 57 acts to stop outdiffusion of silicon into the second titanium layer 60. This second titanium deposition on the amorphous silicon/titanium stack minimizes differential TiSi.sub.2 formations because the silicon selected in TiSi.sub.2 formation originates from amorphous silicon layer 54, rather than from the source region 22 or drain region 23, resulting in better junction integrity. This process saves up to 25% of the area otherwise required in contacts for SRAMS, yielding much improved packing density. Because several devices can share one contact when they need to communicate, the total number of contacts can be greatly reduced. The TiSi.sub.2 LI process of the invention avoids junction integrity problems and rapid dopant outdiffusion.

REFERENCES:
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patent: 4873204 (1989-10-01), Wong et al.
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patent: 4994402 (1991-02-01), Chiu
Chen, et al., "A New Device Interconnect Scheme for Submicron VLSI," IEEE IEDM 1984, pp. 118-121.
de Werdt, et al., "A 1M SRAM with Full CMOS Cell Fabricated . . . ", IEEE IEDM 1987, pp. 532-535.

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