Planar bubble memory circuit fabrication

Details Planar bubble memory circuit fabrication Planar bubble memory circuit fabrication

1980-10-17

1983-10-04

Lusignan, Michael R.

Coating processes

Electrical product produced

Condenser or capacitor

156657, 1566591, 427 90, 427 91, 427 96, 427130, 427131, 427132, 430312, 430314, B44C 122, H01L 21312, C03C 2500, C03C 1500

Patent

active

044078595

ABSTRACT:
A bubble domain device and the method of manufacturing microcircuits having multi-level conductor patterns, which includes forming on a substrate a horizontally extended first level conductor material pattern in pre-configured, relatively overwidth channels defined by a first insulator material layer on the substrate, depositing additional insulator material atop the first level conductor material, and the first insulator layer in channel backfilling relation. The additional insulator material defines a planar surface uniformly spaced above the substrate. The method then includes forming a second upper level conductor material pattern at least partially opposite the first level conductor material pattern and on the additional insulator material surface. The second upper level conductor material pattern being uniformly spaced relative to the substrate by the additional insulator material surface.

REFERENCES:
patent: 3985597 (1976-10-01), Zielinski
patent: 4076575 (1978-02-01), Chang
patent: 4187553 (1980-02-01), Ahn et al.
patent: 4226691 (1980-10-01), Cunningham
patent: 4272348 (1981-06-01), Cox et al.
patent: 4317700 (1982-03-01), Tanaka et al.
patent: 4339305 (1982-07-01), Jones
patent: 4353935 (1982-10-01), Symersky
patent: 4358339 (1982-11-01), Oeffinger et al.
IBM Technical Disclosure Bulletin, vol. 17, No. 2, Jul., 1974.

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