Method of planarization of topologies in integrated circuit stru

Details Method of planarization of topologies in integrated circuit stru Method of planarization of topologies in integrated circuit stru

1988-05-12

1990-10-09

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437233, 437 62, 148DIG51, H01L 21465

Patent

active

049620649

ABSTRACT:
A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: deposition, over an integrated circuit structure having first portions at a height higher than the remainder of the integrated circuit structure, a conformal oxide layer; depositing a layer of a planarizing material such as polysilicon over the conformal oxide layer; polishing the structure a first time to expose the highest portions of the underlying conformal oxide layer; etching the structure a first time with an etchant system capable of removing the conformal oxide preferentially to the planarizing material; further polishing the structure a second time to remove planarizing material left from the first etching step; and then optionally etching the remainder of the structure to remove any remaining planarizing material and the remaining conformal oxide over the raised portions of the underlying integrated circuit structure to provide the desired highly planarized structure.

REFERENCES:
patent: 4662064 (1987-05-01), Hsu
patent: 4789648 (1988-12-01), Chow
Chen, J. Y. et al., "A Fully Recessed Field Isolation Technology Using Photo-CVD Oxide", IEDM, vol. 82, 1982, pp. 233-236.
Shibata, T. et al., "A Simplified Box (Buried-Oxide) Isolation Technology for Megabit Dynamic Memories", IEDM, vol. 83, 1983, pp. 27-30.

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