Method for fabricating a CMOS device with reduced number of phot

Details Method for fabricating a CMOS device with reduced number of phot Method for fabricating a CMOS device with reduced number of phot

1994-11-15

1995-08-08

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437 56, 437 58, 437 41, 148DIG82, H01L 218238

Patent

active

054398347

ABSTRACT:
In a method for fabricating a CMOS device with NMOS and PMOS transistors, patterned nitride films are employed in the source/drain ion implantation procedure to reduce the required number of photolithography steps.

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patent: 5010030 (1991-04-01), Pfiester et al.
patent: 5015595 (1991-05-01), Wollesen
patent: 5024959 (1991-06-01), Pfiester
patent: 5141890 (1992-08-01), Haken
patent: 5234850 (1993-08-01), Liao

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