System for reducing delay for execution subsequent to correctly

Details System for reducing delay for execution subsequent to correctly System for reducing delay for execution subsequent to correctly

1994-08-04

1998-05-12

Kim, Kenneth S.

395382, 395584, 395585, 395587, 3954211, 39542111, G06F 938

Patent

active

RE0357944

ABSTRACT:
A super-scaler processor is disclosed wherein branch-prediction information is provided within an instruction cache memory. Each instruction cache block stored in the instruction cache memory includes branch-prediction information fields in addition to instruction fields, which indicate the address of the instruction block's successor and information indicating the location of a branch instruction within the instruction block. Thus, the next cache block can be easily fetched without waiting on a decoder or execution unit to indicate the proper fetch action to be taken for correctly predicted branching.

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