SIMD processor operating with a plurality of parallel processing

Details SIMD processor operating with a plurality of parallel processing SIMD processor operating with a plurality of parallel processing

1995-06-05

1998-03-17

Coleman, Eric

39580011, G06F 1580

Patent

active

057297584

ABSTRACT:
Three local buses and three composite operation buses are provided in each processing element. An arithmetic logic unit, a multiplier, a bit operator, and an accumulator are connected to respective local buses and the composite operation buses. As a result, each operation unit can transfer data efficiently using a plurality of buses of different functions.

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"Architecuture of SSI-Image Signal Processor for Image Processing", Fukushima et al., Transactions of the Institute of Electronics, Information and Communication Engineers of Japan, 83/12, vol. J66-C, No. 12.

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