Metal working – Method of mechanical manufacture – Assembling or joining
Patent
1981-08-20
1983-10-04
Ozaki, G.
Metal working
Method of mechanical manufacture
Assembling or joining
29569R, 29578, 29591, 148187, 148188, H01L 21225
Patent
active
044070594
ABSTRACT:
Disclosed is a method of producing a semiconductor device, comprising forming an oxidation-resistive insulating film having one or more openings on a semiconductor substrate, forming an impurity-doped polysilicon pattern in at least the opening of the insulating film by using a mask substantially equal in size to the opening, forming a silicon oxide film on the exposed surface of the polysilicon pattern by thermal oxidation, removing the insulating film, and depositing a conductive material and, then, patterning said conductive material layer for forming an interconnection electrode layer insulated from the polysilicon pattern by the silicon oxide film.
REFERENCES:
patent: 4190466 (1980-02-01), Bhattacharyya et al.
patent: 4270262 (1981-06-01), Hori et al.
patent: 4292728 (1981-10-01), Endo
patent: 4317276 (1982-03-01), Heeren et al.
patent: 4322882 (1982-04-01), Vora
patent: 4322883 (1982-04-01), Abbas et al.
patent: 4338139 (1982-07-01), Shinada
D. D. Tang et al., IEDM Tech. Papers, pp. 201-204, (1979), "Sub--Nanosecond Self--Aligned I.sup.2 L/MTL Circuits."
Ozaki G.
Tokyo Shibaura Denki Kabushiki Kaisha
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