Nonvolatile memory device and operating method thereof

Details Nonvolatile memory device and operating method thereof Nonvolatile memory device and operating method thereof

1999-03-23

2000-12-05

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518517, G11C 1134

Patent

active

061575755

ABSTRACT:
There is provided a nonvolatile memory device and an operating method therof which can perform byte erasing and can be implemented high integration. The nonvolatile memory device has a plurality of cells, each including a stacked gate structure of a floating gate and a control gate. The cells are formed in an area where a plurality of bit lines arranged in parallel at specific intervals perpendicularly intersect a plurality of word lines arranged at specific intervals. The cells also include a plurality of source lines, each being arranged in parallel with the bit lines every byte, and a plurality of source select transistors formed in an area where the source lines intersect the word lines. Two cells are connected to a bit line via one bit line contact. Two cells symmetrically arranged with respect to each other and connected to the same bit line via respective bit line contacts share one active source region. The active source region is in parallel with the word line and is connected to the source line via the source select transistor and a source line contact, and the source line is electrically isolated from another source line.

REFERENCES:
patent: 5638327 (1997-06-01), Dallabora et al.
Mukherjee, Satyen, et al., A Single Transistor EEPROM Cell and its Implementation in a 512K CMOS EEPROM, IEDM Technical Digest, Dec. 1985, pp. 616-619.

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