Avalanche programmed floating gate memory cell structure with pr

Static information storage and retrieval – Floating gate – Particular connection

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36518501, G11C 1134

Patent

active

061575682

ABSTRACT:
A non-volatile memory cell structure which includes a floating gate, at least one injection element and a sense transistor. The injection element is at least partially formed in a first polysilicon layer. The floating gate is provided in a second polysilicon layer and capacitively coupled to the reverse breakdown element. The sense transistor is at least partially formed in a region of a semiconductor substrate, and connected to the floating gate. The structure may further comprise a control gate capacitively coupled to the floating gate and may be formed in said first polysilicon layer.

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"Performance Limitations of a Flash E.sup.2 PROM Cell, Programmed with Zener Induced Hot Electrons", by J. Ranaweera, I. Kalastirsky, A. Dibu-Caiole, W.T. Ng, and C.A.T. Salama, Proceedings, of the 15th Annual Non-Volatile Semiconductor Memory Workshop, Paper #2.2 (1997).

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