Pipelined processor which reduces branch instruction interlocks

Details Pipelined processor which reduces branch instruction interlocks Pipelined processor which reduces branch instruction interlocks

1995-11-22

1998-03-17

Lall, Parshotam S.

395380, G06F 938

Patent

active

057297274

ABSTRACT:
A processor for executing branch instructions each including a branch procedure and another procedure includes the following units. A prefetch unit prefetches instructions from memory and updates a prefetch address which is held in the prefetch unit. A control unit controls an execution of the branch procedure and an execution of the other procedure, which follows the execution of the branch procedure. The branch procedure is to write the prefetch address held in the prefetch unit into branch target address. The prefetch unit sequentially prefetches instructions which start at the branch target address when the other procedure is in execution.

REFERENCES:
patent: 4488227 (1984-12-01), Miu et al.
patent: 4933841 (1990-06-01), Mori et al.
patent: 5034880 (1991-07-01), Fong et al.
patent: 5088030 (1992-02-01), Yoshida
patent: 5148532 (1992-09-01), Narita et al.
patent: 5526498 (1996-06-01), Matsuo et al.
"Forced Branching from the Sequencer," IBM Technical Disclosure Bulletin vol. 36, No. 06A, Jun. 1993.
"Performance and the i860 Microprocessor," 8207 IEEE Micro 11 (1991) Oct., No. 5.

Affiliated with

Also associated with

Rating

Pipelined processor which reduces branch instruction interlocks does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pipelined processor which reduces branch instruction interlocks , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipelined processor which reduces branch instruction interlocks will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-966805