Pattern generating apparatus for memory having a logical operati

Details Pattern generating apparatus for memory having a logical operati Pattern generating apparatus for memory having a logical operati

1990-07-18

1992-12-08

Canney, Vincent P.

Excavating

371 24, G01R 3128

Patent

active

051703980

ABSTRACT:
The present invention relates to a test pattern generating apparatus for a memory having a logical operation function. A principal object is to achieve a high speed data writing into an expected value memory and to make it possible to generate a complicated expected data. The apparatus comprises a pattern generator for generating address, data, ALU control and a write control; a tester CPU for generating a data bus and an address bus; an address selector which receives said address and the address bus; a data selector which receives said data and the data bus; an expected value memory which receives an output of the data selector, an output of said address selector and the write control from said pattern generator; an ALU(arithmetic logic unit) which receives the data from the pattern generator and an output of the expected value memory and performs a logical operation under the control of the ALU control, the output being supplied as a write data to the memory unit to be tested; and a comparator which receives an output of the memory unit and compares the output of the memory unit with an expected data from said ALU, the memory unit beign supplied with the address from the pattern generator and a write data from the ALU.

REFERENCES:
patent: 4775977 (1988-10-01), Dehara
patent: 4862460 (1989-08-01), Yamaguchi
patent: 5043988 (1991-08-01), Brglez et al.

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