Pipelined processor for implementing the least-mean-squares algo

Details Pipelined processor for implementing the least-mean-squares algo Pipelined processor for implementing the least-mean-squares algo

1988-12-12

1990-08-07

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 1531

Patent

active

049473638

ABSTRACT:
A filter processor implements the least mean squares (LMS) algorithm in an N tap digital filter in (N+1) time cycles, where N is an integer. A filter structure is shown which is implemented with a processor having an update portion and a convolution portion. A single memory is shared between the two portions, and the same data is concurrently coupled to both portions for concurrent use. The filter may be efficiently pipelined wherein successive adaptive and convolution operations are executed to efficiently implement an N tap filter with a minimum amount of circuity.

REFERENCES:
patent: 4321686 (1982-03-01), Horna
patent: 4754419 (1988-06-01), Iwata
patent: 4802111 (1989-01-01), Barkan et al.
patent: 4829463 (1989-05-01), Kakishita et al.
P. Feintuch, "An Adaptive Recursive LMS Filter", Proceedings of the IEEE, Nov. 1976, pp. 1622-1624, vol. 64, No. 11.
P. Thompson, "A Constrained Recursive Adaptive Filter for Enhancement of Narrowband Signals in White Noise", Conference Regard to the 12th Asilomar Conference on Circuits, Systems and Computers, Nov. 1978, pp. 214-218.

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