Method and apparatus for rounding in high-speed multipliers

Details Method and apparatus for rounding in high-speed multipliers Method and apparatus for rounding in high-speed multipliers

1988-03-31

1992-12-08

Mai, Tan V.

Boots, shoes, and leggings

36471503, G06F 738

Patent

active

051703718

ABSTRACT:
A rounding circuit (10) for converting and rounding an M bit output from an adder array (12) into a N bit binary magnitude representation includes an incrementer (18) which increments the output of the adder array (12) prior to conversion. A borrow calculator (16) generates a select signal to a multiplexer indicating whether covnersion of the M bit number requires a borrow from the upper N bits. The select signal is used to choose between the incremented or non-incremented output. A converter/decrementer (22) converts the selected output of the multiplexer (20) into a binary magnitude number and also computes the magnitude representation decremented by one. A rounding circuitry (24) computes the rounding direction based on a control signal from control circuitry (26). The rounder circuit (10) calculates rounding information for two cases: (a) assuming that no normalization of the converted value is necessary and (b) assuming that normalization of the converted value is necessary. A selector/shifter (28) chooses between the decremented and non-decremented values based on the rounding information.

REFERENCES:
patent: 3816732 (1974-06-01), Jackson
patent: 4293922 (1981-10-01), Davio et al.
patent: 4495593 (1985-01-01), Ware
patent: 4648058 (1987-03-01), Masumoto
Harata et al, "High speed multiplier using a redundant binary adder tree" in Proc. IEEE ICCD'84, Oct. 1984 (pp. 165-170).

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