Self-correcting memory circuit

Details Self-correcting memory circuit Self-correcting memory circuit

1976-03-15

1977-08-30

Thomas, James D.

Boots, shoes, and leggings

340173BB, 235153AM, G06F 1110, G11C 2900

Patent

active

040457796

ABSTRACT:
A circuit for storing data in a random access memory containing one defective bit per word. A separate read-only memory device or programmable logic array is provided to produce an interrupt bit whenever a memory location containing a defective bit is addressed, where a defective bit is defined as one that is stuck at 1 or stuck at 0. If an interrupt bit is generated the data word is read out from memory and compared to the original. If an equality exists, nothing further is required. If there is an inequality the data word is complemented and stored, and a flag bit is set. When data is read from memory, if the flag bit is set, the data word is complemented again before being used.

REFERENCES:
patent: 3350690 (1967-10-01), Rice
patent: 3422402 (1969-01-01), Sakalay
patent: 3568153 (1971-03-01), Kurtz
patent: 3633175 (1972-01-01), Harper
patent: 3675200 (1972-07-01), Bossen
patent: 3685015 (1972-08-01), Bocek
patent: 3753244 (1973-08-01), Sumilas
patent: 3768071 (1973-10-01), Knauft

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