Semiconductor integrated circuit with a testable block

Details Semiconductor integrated circuit with a testable block Semiconductor integrated circuit with a testable block

1996-07-19

1998-03-17

Beausoliel, Jr., Robert W.

Excavating

371 223, G01R 3128

Patent

active

057295530

ABSTRACT:
Three blocks cascaded to one another in an LSI, namely, an input module, a macro module and an output module, are independently tested. A first test circuit is formed with a first multiplexer interposed between the macro module and the output module, and a second multiplexer and a first control register interposed between the input module and the macro module. A second test circuit is similarly formed with third and fourth multiplexers and a second control register. A test input signal of a plurality of bits is supplied to the first multiplexer, and a latched signal of the first control register is supplied to the third multiplexer, thereby allowing a latched signal of the second control register to be output as a test output signal for observation. Thus, testing techniques requiring a small additional circuit and a small number of additional wires for the test can be provided.

REFERENCES:
patent: 3806891 (1974-04-01), Eichelberger et al.
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patent: 5043985 (1991-08-01), Lin et al.
patent: 5392296 (1995-02-01), Suzuki
patent: 5392298 (1995-02-01), Shinjo
patent: 5406567 (1995-04-01), Ogawa
patent: 5504756 (1996-04-01), Kim et al.
Beausang et al., "Incorporation of the BILBO Technique Within an Existing Chip Design", IEEE 1985 Custom Integrated Circuits Conference Proceedings, pp. 328-331.

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