Reducing propagation delays in a programmable device

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

364488, 364490, G06F 1710

Patent

active

057294682

ABSTRACT:
Select sets of a logic function corresponding to an output of a first logic circuit are determined. These select sets are used to obtain a second logic circuit, the logic function corresponding to the output of which is the same as the logic function corresponding to the output of the first logic circuit. A propagation delay through the second logic circuit may be smaller than a corresponding delay through the first logic circuit. Sometimes, such a smaller propagation delay through the second logic circuit results in the second logic circuit having a smaller critical path delay. The second logic circuit may therefore have a greater maximum operating speed than the first logic circuit.

REFERENCES:
patent: 4916627 (1990-04-01), Hathaway
patent: 5055718 (1991-10-01), Galbraith et al.
patent: 5220213 (1993-06-01), Chan et al.
patent: 5237513 (1993-08-01), Kaplan
patent: 5282148 (1994-01-01), Poirot et al.
patent: 5311442 (1994-05-01), Fukushima
patent: 5359537 (1994-10-01), Saucier et al.
patent: 5526276 (1996-06-01), Cox et al.
John P. Fishburn, "LATTIS: An Iterative Speedup Heuristic for Mapped Logic", 29th ACM/IEEE Design Automation Conference, pp. 488-491, (1992).
John P. Fishburn, "A Depth-Decreasing Heuristic for Cominational Logic; or How to Convert A Ripple-Carry Adder into a Carry-Lookahead Adder or Anything In-Between", 27th ACM/IEEE Design Automation Conference, pp. 361-364, (1990).
kanwar Jit Singh, et al., "Timing Optimization of Combinational Logic", Computer Aided Design International Conference, pp. 282-285, (1988).
1994 "Xilinx, The Programmable Logic Data Book", pp. 2-1 through 2-46 (1994).
G. De Micheli, "Technology Mapping of Digital Circuits", IEEE Computer Society Proceedings Advanced Computer Technology, Reliable Systems and Applications, 5th Annual European Computer Conference, Bologna, pp. 580-586 (1991).
R. Brayton, et al., "MIS: A Multiple-Level Logic Optimization System", IEEE Transactions On CAD, vol. CAD-6, pp. 1062-1081 (Nov. 1987).
S. Devadas, et al., "Boolean Decomposition Of Programmable Logic Arrays", IEEE 1988 Custom Integrated Circuits Conference, pp. 2.5.1-2.5.5.
R. Francis, "Chortle: A Technology Mapping Program For Lookup Table-Based Field Programmable Gate Arrays", 27th IEEE Design Automation Conference, pp. 613-619 (1990).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Reducing propagation delays in a programmable device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reducing propagation delays in a programmable device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reducing propagation delays in a programmable device will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-963991

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.