Latch-up resistant CMOS structure

Details Latch-up resistant CMOS structure Latch-up resistant CMOS structure

1985-09-16

1990-08-07

Wojciechowicz, Edward I.

357 49, 357 52, H01L 2702

Patent

active

049472275

ABSTRACT:
A latch-up free CMOS structure and method of fabrication thereof is disclosed. A P-type substrate (40) is appropriately masked to form a plurality of sites in which isolated wells (50) are formed. A thermal oxide layer (56) is grown on the surface of each well (50), and a boron channel stop (62) implanted therearound. Polysilicon semiconductor material (68) is formed within each well, and implant doped to form an N-well (76) of material. The P-substrate (40) is planarized. PMOS transistors are formed within the oxide isolated N-wells (76), while NMOS transistors are formed in the P-substrate (40) outside the wells.

REFERENCES:
patent: 4507158 (1985-03-01), Kamins et al.
patent: 4528462 (1985-07-01), Shackle et al.
patent: 4532003 (1985-07-01), Beasom

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