Shallow trench isolation with self aligned PSG layer

Details Shallow trench isolation with self aligned PSG layer Shallow trench isolation with self aligned PSG layer

1996-10-11

1998-03-17

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257368, 257372, 257374, 257396, 257398, 257399, 257400, 257506, 257509, 257510, 257519, 257525, 257647, H01L 2976, H01L 2900, H01L 2358

Patent

active

057290431

ABSTRACT:
A method for forming trench isolation and in specific shallow trench isolation(STI) using SiO.sub.2 plugs is proposed. The SiO.sub.2 plugs of the STI have a buried phosphorus (P) rich layer introduced during and subsequent to the trench formation to tie up any sodium ionic contamination from processes prior to gate formation. P impurity layer is formed below the surface of the deposited SiO.sub.2 layer. A preferred method for forming the buried P layer is by shallow implantation in a vertical direction into the deposited SiO.sub.2 layer prior to planarization. The process is self aligned to the trench isolation regions.

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S. M. Sze, "Physics of Semiconductor Devices" 2nd edition, John Wiley & Sons, 1981, pp. 372-396.

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