Method for forming a transistor and a capacitor for use in a ver

Details Method for forming a transistor and a capacitor for use in a ver Method for forming a transistor and a capacitor for use in a ver

1992-03-23

1993-10-26

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437919, 437203, H01L 2170, H01L 2700

Patent

active

052565882

ABSTRACT:
A method for forming a transistor and a capacitor to provide, in one form, a DRAM cell (10). The capacitor of cell (10) is formed within a substrate (12). The capacitor has a first capacitor electrode (16) and a second capacitor electrode (20). A dielectric layer (18) is formed as an inter-electrode capacitor dielectric. A first transistor current electrode (36) is formed overlying and electrically connected to the first capacitor electrode (16). A channel region (38) is formed overlying the first transistor current electrode (36). A second transistor current electrode (40) is formed overlying the channel region (38). A conductive layer (30) is formed laterally adjacent the channel region (38) and isolated from the substrate (12) by dielectric layers (22 and 28). A conductive layer (30) functions as a gate electrode for the transistor and a sidewall dielectric (34) functions as a gate dielectric.

REFERENCES:
patent: 4686552 (1987-08-01), Teng et al.
patent: 4713678 (1987-12-01), Womack et al.
patent: 5047815 (1991-09-01), Yasuhira et al.
patent: 5055898 (1991-10-01), Beilstein et al.
patent: 5073515 (1991-12-01), Roehl et al.
patent: 5100822 (1992-03-01), Mitani
patent: 5111259 (1992-05-01), Teng et al.
patent: 5126280 (1992-06-01), Chan et al.
A Trench Transistor Cross-Point DRAM Cell, by W. F. Richardson et al., was published and presented at the IEEE IEDM Conference 1985, pp. 714-717.

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