Methods of patterning and manufacturing semiconductor devices

Details Methods of patterning and manufacturing semiconductor devices Methods of patterning and manufacturing semiconductor devices

1992-07-10

1993-10-26

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 60, 437228, 437235, 437919, 148DIG138, H01L 2170

Patent

active

052565874

ABSTRACT:
Methods of hyperfine patterning and manufacturing semiconductor devices. Steps in accordance with the present invention include coating a hemisphere particle layer having hills and valleys on a layer to be etched, the hemisphere particle layer having an etch selectivity higher than that of the first layer, filling the valleys of the hemisphere particle layer with a second layer having an etch selectivity higher than that of the hemisphere particle layer, and etching back the hills of the hemisphere particle layer to expose the first layer by using the second layer as a mask, and etching the first layer. By virtue of the hemisphere particle layer having alternating hills and valleys, it is possible to accomplish a hyperfine patterning of about 0.1 .mu.m. Since the mean size and the density of hills and valleys of the hemisphere layer can be controlled, the pattern size also can be controlled. Where the present invention is applied to capacitors of semiconductor memory elements, the capacitor node surface area can be increased, depending on the etched back depth of a polysilicon layer.

REFERENCES:
patent: 4545852 (1985-10-01), Bartom
patent: 5023204 (1991-06-01), Adachi et al.
patent: 5134086 (1992-07-01), Ahm
Electrical Characterization of Textured Interpoly Capacitors for Advanced Stacked Drams by: Pierre C. Fazan and Akram Ditali; IEDM 1990, pp. 27.5.1-27.5.4.
Rugged Surface Poly-si Electrode and Low Temperature Deposited Si.sub.3 N.sub.4 for 64 MBIT and Beyond STC Dram Cell by: M. Yoshimaru, J. Miyano, N. Inoue, A. Sakamoto, S. You, H. Tamura and M. Ino; IEDM 1990, pp. 27.4.1-27.4.4.
A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64Mb DRAMs by: M. Sakao, N. Kasai, T. Ishijima, E. Ikawa, H. Watanabe, K. Terada and T. Kikkawa; IEDM 1990; pp. 27.3.1-27.3.4.

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