Doped well structure and method for semiconductor technologies

Fishing – trapping – and vermin destroying

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437 56, 437 61, 437 46, 437228, 148DIG112, H01R 2122, H01L 21302

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active

052565637

ABSTRACT:
A method of forming doped wells 24 and 30 in a semiconductor layer is disclosed herein. In a preferred embodiment, an oxide layer 16 is formed on the surface of a silicon layer 14. A nitride layer 18 is then formed on the oxide layer 16 and is patterned and etched to define a first well region 24. The first well region 24 is then doped, for example with phosphorus or boron. A resist layer 26 is formed over the first well region 24 and over a portion of the nitride layer 18 after which a portion of the nitride layer 18 not beneath the resist layer 26 is removed to expose a second well region 30. The second well region 30 is then doped. After the remaining portion the resist layer 26 is removed, an oxide layer 32 is formed over the first 24 and second 30 well regions while the surface 38 over the region 36 separating the well regions is left bare. The semiconductor wafer 10 is then heated in a nitridizing environment (e.g., ammonia ambient) such that dopants tend to diffuse into the silicon layer 14 with enhanced vertical diffusivities but reduced lateral diffusivities.

REFERENCES:
patent: 4786609 (1988-11-01), Chen
patent: 4904613 (1990-02-01), Coe et al.
patent: 4968639 (1990-11-01), Bergonzoni
M. M. Moslehi et al., "Compositional Studies of Thermally Nitrided Silicon Dioxide (Nitroxide)", J. Electrochem. Soc.: Solid-State Science and Technology, vol. 132, No. 9, Sep. 1985, pp. 2189-2197.
M. M. Moslehi et al., "Thermal Nitridation of Si and SiO.sub.2 for VLSI", IEEE Transactions on Electron Devices, vol. Ed-32, No. 2, Feb. 1985, pp. 106-123.
M. M. Moslehi et al., "Rapid thermal nitridation of SiO.sub.2 for nitroxide thin dielectrics", Appl. Phys. Lett. 47, vol. 47, No. 10, Nov. 15, 1985, pp. 1113-1115.

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