Method of forming a bit line over capacitor array of memory cell

Details Method of forming a bit line over capacitor array of memory cell Method of forming a bit line over capacitor array of memory cell

1993-04-14

1994-08-16

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437233, 437919, H01L 2172

Patent

active

053387007

ABSTRACT:
A method of forming a bit line over capacitor array of memory cells includes providing first conductive material pillars within first contact openings downwardly to active (source/drain) areas for ultimate connection with bit lines. A covering layer of insulating material is provided over the first pillars, and contact openings provided therethrough to electrically connect with other active (source/drain) areas for formation of capacitors. Capacitors are then provided within the capacitor contact openings. An overlying layer of insulating material is then provided over the covering layer of insulating material and over the capacitors. Bit line contact openings are then provided through the overlying layer and the covering layer to the first pillar upper surfaces. Then, a digit line layer of conductive material is provided atop the wafer and within the bit line contact openings, the digit line layer electrically connecting with the first pillar upper surfaces.

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Miyagawa et al., "Two stip Deposited Rugged Surface Storagenode and Self Aligned Bitline-Contact Penetrating Cellplate for 64Mb DRAM STC Cell," pp. 9-10, (no date).

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