Method of generating active semiconductor structures by means of

Details Method of generating active semiconductor structures by means of Method of generating active semiconductor structures by means of

1993-05-03

1994-08-16

Kunemund, Robert

Fishing, trapping, and vermin destroying

437 61, 437133, H01L 21265

Patent

active

053386922

ABSTRACT:
A unipolar electronic component is proposed with a quasi one dimensional carrier channel which has all the characteristics of an FET. This component can be very simply produced, has "self-alignment" and linear gates with a low capacity in place of planar gates. In this way a very high operating frequency of the component is possible. The structure comprises an initially homogenous 2D-layer with a high carrier mobility which is formed by epitaxy of for example GaAs. The implantation of focussed ions (for example Ga.sup.+ with 100 keV) locally destroys the conductivity of the electron layer. The irradiated regions remain insulating at low temperature or room temperature even after illuminating the cristal with bandgap radiation. The writing in of the insulating layer is carried out along two paths on the chip so that the 2D-carrier layer is subdivided into three regions insulated from one another. The source and drain are only connected by a narrow channel 44 the width of which is continuously tunable by a gate potential which is simultaneously applied to the two gate regions relative to the source, so that a pronounced change of the carrier concentration and thus of the channel resistance arises. The specification also describes integrated circuits made using the same methods.

REFERENCES:
patent: 3655457 (1972-04-01), Duffy et al.
patent: 3696274 (1972-10-01), Davis
patent: 4325073 (1982-04-01), Hughes
patent: 4325181 (1982-04-01), Yoder
patent: 4460910 (1984-07-01), Chappell
patent: 4771013 (1988-09-01), Curan
patent: 4796068 (1989-01-01), Katayama et al.
patent: 4853341 (1989-08-01), Nishioka et al.
patent: 4989052 (1991-01-01), Okada et al.
patent: 5141879 (1992-08-01), Goronkin
Wieck et al., "In-Plane-Gated Quantum Wire Transistor Fabricated with Dirly Written Focused Ion Beams", Appl. Phys. Lett., 56(10), Mar. 5, 1990, pp. 928-930.
Hirayama et al., ". . . Ballistic One-Dimensional Channels Controlled by a Gate Electrode", Appl. Phys. Lett. 54(25), Jun. 19, 1989, pp. 2556-2558.
Hirayama et al., ". . . Narrow Channels Constricted in GaAs by Highly Resistive Ga-Implanted Regions", Phys. Review B, 39(8) Mar. 15, 1989, pp. 5535-5537.
Nakamura et al., ". . . One-Dimensional Channels Made by Focused Ion Beams," Appl. Phys. Lett., 56(4), Jan. 22, 1990, pp. 385-387.
Susumu Namba, Focused Ion Bean Processing, (1989) 504-510 Nuclear Instruments and Methods in Physics Research B39.
IBM Technical Disclosure Bulletin, vol. 29, No. 5, Oct. 1986 Semiconductor Two-dimensional Hold Gas Heterostructures.
D. D'Avanzo, Proton Isolation for GaAs Integrated Circuits, vol. ED-29, No. 7, Jul. 1982, IEE Transactions on Electron Devices.
Demel, T., et al., "One-dimensional Electronic Systems in Ultrafine Mesa-etched Single and Multiple Quantum Well Wires," Appl. Phys. Lett. 53 (22), Nov. 28, 1988, pp. 2176-2178.
Moreland, J., et al., "Air as an Adjustable Insulator for C-V and G-V Analysis of Semiconductor Surfaces," Appl. Phys. Lett. 45 (1), Jul. 1, 1984, pp. 104-105.
Skocpol, W. J., et al., "Quantum Transport in Narrow Mosfet Channels," Surface Science 170 (1986) pp. 1-13.
Deng, X., "Oxygen Ion Beam Modification of GaAs," 2107 Nuclear Instruments & Methods in Physics Research, vols. 209/210, May 1983, pp. 657-661.
Hiramoto, T., "Fabrication of One-Dimensional GaAs Wires by Focused Ion Beam Implantation," J. Vac. Sci. Technol. B 6 (3), May/Jun. 1988, pp. 1014-1017.
Miyauchi, E., "Application of Focused Ion Beam Technology to Maskless Ion Implantation in a Molecular Beam Epitaxy Grown GaAs or AlGaAs Epitaxial Layer for Three-Dimensional Pattern Doping Crystal Growth," J. Vac. Sci. Technol. A 4 (3), May/Jun. 1986, pp. 933-938.
Grambow, P., et al., "Preparation of One-Dimensional Single and Multi-Layered Quantum Wire Structures by Ultrafine Deep Mesa Etching Techniques," Microelectronic Engineering 9 (1989) pp. 357-360.
Eden, R. C., et al., "Integrated Circuits: The Case for Gallium Arsenide," IEEE Spectrum, Dec. 1983, pp. 30-37.

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