Method of testing a logic system and a logic system for putting

Details Method of testing a logic system and a logic system for putting Method of testing a logic system and a logic system for putting

1981-05-26

1983-12-27

Malzahn, David H.

Excavating

324 73AT, G06F 1122

Patent

active

044235097

ABSTRACT:
A method for testing a logic system of the type having points not directly accessible from the exterior, and logic systems including means for carrying out the method. A particular logic state may for test purposes be applied (set) at a particular, normally-inaccessible point in the system; or the logic state at a particular, normally-inaccessible point in the system may be sampled. To accomplish these functions, there are a plurality of flip-flops and associated selective gating circuitry, for example AND-OR select gates, arranged selectively either to connect the flip-flops in series to form a shift register configuration whereby data defining particular logic states to be set, or particular logic states which have been sampled, may be clocked in or clocked out by accessing only the input of the first flip-flop or the output of the last flip-flop; or to connect the inputs and outputs of the various flip-flops to particular points in the system for the purposes of setting and sampling logic states. The logic system may, for example, be either a single integrated circuit chip, or a circuit module having a limited number of external connections.

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Williams "Testing of LSI Logic Circuits Containing Imbedded Shift Arrays" IBM Tech. Disclosure Bulletin, vol. 20, No. 18, Mar. 1978 pp. 4021-4022.
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RCA 1974 COS/MOS Digital Integrated Circuit Databook No. SSD-203 B pp. 100-102.

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