System fpr transferring data between two buses using control reg

Details System fpr transferring data between two buses using control reg System fpr transferring data between two buses using control reg

1994-04-25

1997-01-28

Lee, Thomas C.

G06F 1502

Patent

active

055985793

ABSTRACT:
A computer system which includes a DMA controller on the local I/O unit which can be programmed by either the host processor or the local processor. Semaphore flags and lock bits are provided to allow determination of control of the local DMA controller and for passing information. Additionally, data alignment and padding circuitry is provided. The circuitry is informed of the logical data arrangement desired or utilized by the host processor or other devices and knows the data arrangement of the local processor. The circuitry properly obtains and realigns the data based on the transfer direction and data arrangement. The circuitry further properly zero pads the data when realignment is such that padding is necessary.

REFERENCES:
patent: 4380798 (1983-04-01), Shannon et al.
patent: 4594657 (1986-06-01), Byrns
patent: 4754398 (1988-06-01), Pribnow
patent: 4809269 (1989-02-01), Gulick
patent: 5159686 (1992-10-01), Chastain et al.
patent: 5339443 (1994-08-01), Lockwood
patent: 5367690 (1994-11-01), Schiffleger
patent: 5434970 (1995-07-01), Schiffleger

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