Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1989-11-14
1991-05-07
Popek, Joseph A.
Static information storage and retrieval
Addressing
Plural blocks or banks
36523006, 36518911, G11C 1134
Patent
active
050142461
ABSTRACT:
A memory cell array (10) is divided into four blocks. Each block comprises a memory cell array block (10aand a memory cell array block (10b). A sense amplifier block (20) is disposed between the memory cell array blocks (10a) and (10b). Each sense amplifier block (20) is connected to the memory cell array blocks (10a) and (10b) via switching circuits (80a, 80b), respectively. Four decoders (51) are provided corresponding to the four blocks. The four decoders (51) are commonly provided with a driver (52) generating a high level driving signal. Each decoder (51) is responsive to an address signal for supplying a driving signal from the driver (52) to either one of the switching circuits (80a, 80b) and for applying a ground potential to the other one of the circuits. Accordingly, the sense amplifier block (20) is connected to either one of the memory cell array blocks (10a, 10b ).
REFERENCES:
patent: 4569036 (1986-02-01), Fujii et al.
Masaki Kumanoya et al., "FAM 17.2: A 90ns 1Mb Dram with Multi-Bit Test Mode," IEEE International Solid-State Circuits Conference, 1985, pp. 240-241.
Dosaka Katsumi
Inoue Yoshinori
Komatsu Takahiro
Konishi Yasuhiro
Kumanoya Masaki
Mitsubishi Denki & Kabushiki Kaisha
Popek Joseph A.
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