Wiring structures for semiconductor memory device

Details Wiring structures for semiconductor memory device Wiring structures for semiconductor memory device

1989-04-12

1991-05-07

Hille, Rolf

357 236, 357 40, 357 45, 357 71, H01L 2348

Patent

active

050141104

ABSTRACT:
A semiconductor memory comprises a semiconductor substrate (1), word lines (200) and bit lines (3a, 3b), memory cells and sense amplifier (SA). The semiconductor substrate (1) has a major surface. The word lines (200) and bit lines (3a, 3b) intersect each other on the major surface of the substrate (1). The bit lines (3a, 3b) are arranged in the form of parallel bit line pairs. The memory cells are arranged at intersections of the word lines (200) and the bit lines (3a, 3b). The sense amplifier (SA) senses voltage differentials of the bit line pairs. Corresponding sections of the bit lines (3a, 3b) of the bit line pair are interchanged laterally on the substrate (1) along the length of the bit line pair. Corresponding sections of the bit lines (3a, 3b) of each bit line pair have the same number of joining portions (10) respectively. It is possible to provide a semiconductor memory device having a wiring structure capable of minimizing an influence due to the noise from the adjacent wiring line.

REFERENCES:
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IEEE Journal of Solid-State Circuit, vol. SC-22, No. 5, Oct. '87, "A 65-ns 4-Mbit CMOS DRAM with a Twisted Driveline Sense Amplifier", by Kimura et al.
Patrick W. Bosshart et al., "A 553K-Transistor LISP Processor Chip", 1987 IEEE International Solid State Circuits Conference, Feb. 26, 1987., pp. 202-203.
"Double-Traversing Pseudo-Bitline Design for Cross-Point Memory Cells", IBM Technical Disclosure Bulletin, vol. 30, No. 11, Apr. 1988, pp. 246-248.

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