Process for fabricating complementary contactless vertical bipol

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357 35, 357 49, 357 56, 357 59, H01L 2702, H01L 2972, H01L 2712

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active

050141074

ABSTRACT:
A complementary NPN and PNP contactless vertical transistor structure is formed by a process that includes the steps of providing: (1) a buried layer and P- tub for NPN; (2) a channel stopper for NPN, and a buried layer for PNP; (3) isolation oxide for NPN and PNP; (4) a sink for NPN, and a ground for PNP; (5) a base for NPN, and a sink for PNP; (6) a base for PNP; (7) a N+ poly implant for NPN emitter and PNP extrinsic base; (8) a P+ poly implant for NPN extrinsic base and PNP emitter; (9) poly definition; (10) silicide exclusion for resistors and diodes; (11) contacts; (12) first metal; (13) vias; (14) second metal; and (15) scratch protection.

REFERENCES:
patent: 3648125 (1972-03-01), Peltzer
patent: 3912555 (1975-10-01), Tsuyuki
patent: 4038680 (1977-07-01), Yagi et al.
patent: 4051506 (1977-09-01), Hurie
patent: 4260999 (1987-04-01), Yoshioka
patent: 4484211 (1984-11-01), Takemoto et al.
patent: 4510676 (1985-04-01), Anantha et al.
patent: 4512816 (1985-04-01), Ramde et al.
patent: 4539744 (1985-09-01), Burton
patent: 4567058 (1986-01-01), Koh
patent: 4583106 (1986-04-01), Anantha et al.
patent: 4593458 (1986-06-01), Adler
patent: 4609568 (1986-09-01), Koh et al.
patent: 4764480 (1988-08-01), Vora
Marcoux et al., "Methods of End Point Detection for Plasma Etching", Solid State Technology (1981), 24:115-122.
Hoya Electronics Co., Ltd., "Etching End-Point Determination", Chemical Abstracts, vol. 99, 1983, pp. 588, Abstract No. 15042h.
Lee et al., "A Study of Tungsten Etchback for Contact and Via Fill Applications", 1987 Proceedings 4th Int'l IEEE VLSI Multilevel Interconnection Conference, Santa Clara, Ca., 15th-16th Jun., 1987, pp. 193-199.
Adams et al., "Planarization of Phosphorus-Doped Silicon Dioxide", J. Electrochem. Soc. (1981), 128:423-429.
Picard et al., "Plasma Etching of Refractory Metals (W, Mo, Ta) and Silicon in SF.sub.6 and SF.sub.6 -O.sub.2. An Analysis of the Reaction Products", Plasma Chemistry and Plasma Processing (1985), 5: 333-351.
Chow et al., "Plasma Etching of Refractory Gates for VLSI Applications", J. Electrochem. Soc. (1984), 131:2325-2335.
Proceedings of the 1986 Bipolar Circuit and Technology Meeting, 9/11-9/12/86, pp. 33-34, IEEE, U.S. Kapoor et al.: "An Improved Single-Poly Bipolar Technology for Linear/Digital Applications".
Proceedings of the IEEE 1985 Custom Integrated Circuits Conference, 5/20-5/23/85, pp. 184-187, U.S. Kapoor et al.: "A High-Speed, High-Density Single-Poly ECL Technology for Linear/Digital Applications".
Electronics, 9/4/86, pp. 55-59, "Fairchild's Radical Process for Building Bipolar VLSI".
Electronics, Jun., 1987, pp. 67-77, "ECL's Worldwide Drive to Take Over TTL Sockets".

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