Electrical pulse counters – pulse dividers – or shift registers: c – Charge transfer device – Particular input or output means
Patent
1988-02-04
1991-01-08
Miller, Stanley D.
Electrical pulse counters, pulse dividers, or shift registers: c
Charge transfer device
Particular input or output means
377 58, 377 62, 307574, 307578, 3072966, 357 24, G11C 1928, H01L 2978
Patent
active
049842560
ABSTRACT:
A floating diffusion region and a drain region are formed separately from each other in a substrate. A reset electrode is arranged above an area located between the drain region and the floating diffusion region. A voltage step-up circuit having a reference voltage generator receiving a power source voltage for generating a reference voltage and a step-up circuit receiving a clock pulse for applying a voltage level of the clock pulse to the reference voltage applies a voltage to the drain region. The gate of a conversion E type MOS transistor for converting and outputting the charge stored in the floating diffusion region to a signal having a voltage level proportional to the charge amount is connected to the floating diffusion region. The reference voltage generator has D type MOS transistor and E type MOS transistor connected in cascade for producing the reference voltage of the value corresponding to the variation from a process center of the manufacturing process of this charge transfer device. The D type MOS transsitor has the same conductivity type and construction as the MOS transistor formed of the reset electrode, the floating diffusion region and the drain region. The E type MOS transistor has the same conductivity type as the conversion E type MOS transistor.
REFERENCES:
patent: 3955101 (1976-05-01), Amelio et al.
patent: 4100437 (1978-07-01), Hoff, Jr.
patent: 4180807 (1979-12-01), Eichelberger et al.
patent: 4479067 (1984-10-01), Fujita
patent: 4614882 (1986-09-01), Parker et al.
patent: 4627083 (1986-12-01), Pelgrom et al.
patent: 4633101 (1986-12-01), Masuda et al.
patent: 4649289 (1987-03-01), Nakano
patent: 4686451 (1987-08-01), Li et al.
patent: 4709168 (1987-11-01), Kamuro et al.
patent: 4719372 (1988-01-01), Chappell et al.
patent: 4771194 (1988-09-01), van Zeghbroeck
patent: 4809307 (1989-02-01), Sakaue et al.
Japanese Patent Disclosure (Kokai) No. 59-132668, Imai et al., Jul. 30, 1984.
Japanese Patent Disclosure (Kokai) No. 61-216473, Kimata, Sep. 26, 1986.
Duong Tai V.
Kabushiki Kaisha Toshiba
Miller Stanley D.
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