Increased surface area for DRAM, storage node capacitors, using

Details Increased surface area for DRAM, storage node capacitors, using Increased surface area for DRAM, storage node capacitors, using

1995-05-25

1997-01-28

Tsai, Jey

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

055977545

ABSTRACT:
A process for fabricating a stacked capacitor, DRAM, device, with an optimized lower electrode structure, has been developed. The surface area of the lower electrode has been increased by using a specific polysilicon deposition process, featuring the use of Si2H6, followed by specific insitu anneals, initially in nitrogen, and then in a vacuum.

REFERENCES:
patent: 5278091 (1994-01-01), Fazan et al.
patent: 5286668 (1994-02-01), Chou
patent: 5290729 (1994-03-01), Hayashide et al.
patent: 5366917 (1994-11-01), Watanabe et al.
patent: 5407534 (1995-04-01), Thakur

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