Programmable state machines connectable in a reconfiguration swi

Details Programmable state machines connectable in a reconfiguration swi Programmable state machines connectable in a reconfiguration swi

1988-12-02

1991-01-08

Zache, Raulfe B.

Boots, shoes, and leggings

364931, 3649311, 3649493, 3649494, G06F 1516

Patent

active

049841920

ABSTRACT:
A programmable element (PE) for implementing programmable logic circuits includes a run address register, a load address register and a random access memory (RAM). The RAM is initialized with a state transition table using the load address register. After RAM initialization, and at each clock transition, the run address register is loaded with external inputs and a present state. The present state is received as the next state output of the RAM from internal feedback lines from the RAM output to the run address register inputs. The RAM output is divided into a next state which is stored in the internal feedback lines and element data outputs to an destination external to the programmable element. A state processor (SP) for implementing complex programmable logic circuits includes a plurality of programmable elements and a matrix switch. The matrix switch provides external feedback for programmable elements. In addition, any programmable output may be routed to any programmable element input. A hierarchical network of state processors for implementing programmable logic systems includes a plurality of state processors and a plurality of matrix switches. Within the hierarchical network any state processor input can receive any state processor output.

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