Computer system speed control at continuous processor speed

Details Computer system speed control at continuous processor speed Computer system speed control at continuous processor speed

1991-03-21

1992-06-23

Shaw, Gareth D.

395550, G06F 1500

Patent

active

051250888

ABSTRACT:
A personal computer is disclosed having a high speed microprocessor which executes in a variety of selectable speed modes to provide greater compatibility with application programs written for slower speed microprocessors. A logic means is included responsive to a speed select signal which does not change the speed of the microprocessor oscillator (clock) but rather changes the length of a wait state or "STOP" state of the microprocessor. In the STOP state the microprocessor (CPU) does not run bus cycles until the timer times out thereby releasing the CPU STOP. By varying the length of the time delay of the one-shot timer, the microprocessor simulates microprocessor speed changes which have the appearance of earlier generation computers with older microprocessors. A logic means permits a computer operator to select a speed which the operator wants the microprocessor to "simulate" and also permits the operator to select a type of older microprocessor which the operator wants the new high speed microprocessor to "simulate." A means of automatically varying the apparent microprocessor speed is also disclosed when data transfer from a floppy diskette are detected.

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"8257/8257-5 Programmable DMA Controller," Intel Corporation, 1974; pp. 6-115 to 6-131.
IBM Technical Disclosure Bulletin, vol. 15, No. 1, Jun. 1972, pp. 111-113.

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