Process for fabricating a DRAM array having feature widths that

Details Process for fabricating a DRAM array having feature widths that Process for fabricating a DRAM array having feature widths that

1990-07-18

1991-05-07

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 38, 437 47, 437 51, 437191, 437192, 437200, 437228, 437233, 437235, 437919, H01L 2170

Patent

active

050136801

ABSTRACT:
A process for creating a DRAM array having feature widths that transcend the resolution limit of the employed photolithographic process using only five photomasking steps. The process involves the following steps: creation of a half-pitch hard-material mask that is used to etch a series of equidistanty-spaced isolation trenches in a silicon substrate; filling the isolation trenches with insulative material; creation of a hard-material mask consisting of strips that are 1-1/2F in width, separated by spaces that are 1/2F in width, that is used to etch a matrix of storage trenches; angled implantation of a N-type impurity in the storage trench walls; another anisotropic etch to deepen the storage trenches; deposition of a capacitor dielectric layer; deposition of a protective polysilicon layer on top of the dielectric layer; removal of the dielectric layer and the protective polysilicon layer at the bottom of each storage trench with a further anisotropic etch; filling the storage trenches with in-situ-doped polysilicon; planarization down to the substrate level; creation of an access gate on opposite sides of each storage trench, in addition to wordlines which interconnect gates within array columns by anisotropically etching a conformal conductive layer that has been deposited on top of oxide-silicon mesas that run perpendicular to the isolation trenches and are centered between the rows of storage trenches, the oxide-silicon mesas having been created with an etch using a photoresist mask consisting of a series of parallel strips that have been laid down with minimum feature and space width, then plasma etched to 3/4F; creation of source and drains with an N-type implant; and anisotropically etching the metal layer to create bitlines along the sidewalls of the oxide mesas.

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Nicky C. C. Lu, "Advanced Cell Structures for Dynamic RAMS", IEEE Circuits and Devices Magazine, Jan. 1989, pp. 27-36.

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