Process for reduced emitter-base capacitance in bipolar transist

Fishing – trapping – and vermin destroying

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Other Related Categories

437909, 437 28, 437979, 148DIG10, 148DIG11, H01L 21331

Type

Patent

Status

active

Patent number

050136712

Description

ABSTRACT:
A process and structure for resolving the divergent etching requirements of a relatively thick base oxide (62) and a relatively thin gate oxide (64) in a BiCMOS integrated circuit. The necessity of etching base oxide (62) is eliminated by extending nitride mask (58) over the extrinsic base region (86) so that the relatively thick base oxide (62) only covers intrinsic base region (60) and tab region (61). Base oxide (62) at tab region (61) is partially etched in the course of forming sidewall oxide filaments (78), resulting in the residual tab oxide (62'). An extrinsic base implant is performed in extrinsic base region (86) and tab region (61), with the presence of residual tab oxide (62') affecting the profile of the implant so that it is stepped. The resulting structure, after an anneal, is extrinsic base (87'), an intrinsic base (63) (formed prior to the extrinsic base implant), and an overlap region (88') common to both. Extrinsic base ( 87') has a relatively greater dopant concentration compared to intrinsic base region (63). The dopant concentration in overlap region (88') is substantially that of extrinsic base (87'). The overlap region (88') insures adequate conductivity link-up between the extrinsic base (87') and the intrinsic base (63). Since no thick base oxide (62) is ever formed in extrinsic base region (86), no undesirable heavy etch is required in extrinsic base region (86), such a heavy etch being undesirable because of the necessity of an extra processing step for masking areas containing the relatively thinner oxide (64). Thus, a processing step is eliminated and yet adequate conductivity link-up between extrinsic base (87') and intrinsic base (63) is achieved via overlap region (88').

REFERENCES:
patent: 4503603 (1985-03-01), Blossfield
patent: 4529456 (1985-07-01), Anzai et al.
patent: 4566175 (1986-01-01), Smayling et al.
patent: 4616405 (1986-10-01), Yasuoka
patent: 4637125 (1987-01-01), Iwasaki et al.
patent: 4678936 (1987-07-01), Holloway
patent: 4694562 (1987-09-01), Iwasaki et al.
patent: 4710791 (1987-12-01), Shirato et al.
patent: 4737472 (1988-04-01), Schaber et al.
patent: 4745080 (1988-05-01), Scovell et al.
patent: 4752589 (1988-06-01), Schaber
patent: 4816423 (1989-03-01), Havemann
patent: 4874717 (1989-10-01), Neppl et al.
patent: 4890147 (1989-12-01), Teng et al.
Cuthbertson et al., "Self-Aligned Transistors with Polysilicon Emitters for Bipolar VLSI", IEEE Trans. on Electron Device, vol. ED-32, No. 2, Feb. 1985, pp. 242-247.
High-Speed BiCMOS Technology with a Buried Twin Well Structure, Ikeda et al., pp. 1304-1309, Jun., 1987, (IEEE Transactions on Electron Devices, vol. ED-34, #6).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Process for reduced emitter-base capacitance in bipolar transist does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for reduced emitter-base capacitance in bipolar transist, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for reduced emitter-base capacitance in bipolar transist will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-939269

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.