Patent
1989-01-13
1991-01-08
Mintel, William
357 40, 357 45, 357 43, 357 54, 357 68, 357 65, 357 71, H01L 2702
Patent
active
049840509
ABSTRACT:
A gate array type integrated circuit semiconductor device includes a semiconductor substrate, in a basic cell forming portion of which are formed a plurality of impurity regions of basic circuit elements. The impurity regions form a plurality of basic cells. A field insulating layer is also formed on the substrate, which is partially embedded in the major surface of the substrate and is formed entirely on a wiring channel forming portion of the substrate and selectively on the basic cell forming portion of the same to surround each of the impurity regions. An insulating film is formed on the field insulating layer. A wiring structure is provided, which includes mutual wirings formed of a first level conductive layer, internal wirings, and interconnecting wirings formed of a second level conductive layer higher than the first level conductive layer. Each of the mutual wirings is formed only on the insulating film formed on the wiring channel forming portion and is connected to the impurity regions through the interconnecting and internal wirings.
REFERENCES:
patent: 3667006 (1972-05-01), Ruegg
patent: 3708691 (1973-01-01), Gilbert
patent: 4233618 (1980-11-01), Genesi
patent: 4417265 (1983-11-01), Murkland et al.
patent: 4737836 (1988-04-01), Askin et al.
Mintel William
NEC Corporation
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