Process and circuit arrangement for addressing the memories of a

Details Process and circuit arrangement for addressing the memories of a Process and circuit arrangement for addressing the memories of a

1987-06-29

1989-05-09

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 1206, G06F 1516

Patent

active

048294209

ABSTRACT:
A process and a circuit arrangement for the automatic direct addressing of any desired memory location in the memories of a plurality of data processing units interconnected through a common bus by use of a single-step addressing technique is disclosed. The size of the memories used in the various processing units may be different. Addresses may be internally stored in the memories according to one of two addressing schemes. In a data processing unit initiating a data transmission connection, the external memory address of the desired memory location to be addressed is generated from an internally stored address and is transmitted to the bus system. This external address is received in each data processing unit, which performs an address calculation to determine whether the specified external address is within its volume or range of addresses.

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