Method and apparatus for verifying the state of a plurality of e

Details Method and apparatus for verifying the state of a plurality of e Method and apparatus for verifying the state of a plurality of e

1991-07-29

1992-06-23

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular biasing

36518907, 365201, G11C 1140

Patent

active

051249456

ABSTRACT:
Apparatus for verifying the state of a plurality of electrically programmable memory cells (30-70) includes first and second memory cells (36, 38) each having current paths with first and second ends. A memory cell state sense node (BL2) is coupled to the first ends. A first array source node (82) is coupled to a second end of the current path of the first cell (36). A second array source node (84) is coupled to a second end of the current path of the second cell (38). First circuitry (160-198) is provided for sensing a program verify state (DATA, WE). Decoded ground circuitry (150, 144, 142) couples a selected one of the first and second array source nodes (140) to a low voltage source (Vss) in response to the first circuitry sensing a program verify state (DATA, WE). Second circuitry (130, 138, 134) selectively isolates at least a nonselected one of the first and second array source nodes (82, 84) from the voltage bias source in response to the first circuitry (160-198 ) sensing a program verify state (DATA, WE).

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Ashmore et al., "A 20ns 1 Mb CMOS Burst Mode EEPROM" ISSCC 89, 02/15/89 pp. 40,41.

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