1988-04-29
1991-01-08
Sikes, William L.
357 51, H01L 2990
Patent
active
049840312
ABSTRACT:
In an integrated circuit arrangement with a protective arrangement at least partially integrated into it and protecting the integrated circuit arrangement from high-energy electrical faults, the protective arrangement has an ohmic resistance in the form of one or more resistance areas that is designed so as to absorb a major proportion of the energy from electrical faults in the event of limit loads and distribute the heat generated within it by the energy absorption over a surface of the protective arrangement such that the protective arrangement affected by the heat energy of the ohmic resistance is not thermally overloaded. Furthermore, the protective arrangement has a voltage-limiting element or several voltage-limiting elements to limit the interference voltage.
REFERENCES:
patent: 3562547 (1971-02-01), Brode et al.
patent: 3590340 (1971-06-01), Kubo et al.
patent: 3619725 (1971-11-01), Soden et al.
patent: 4135295 (1979-01-01), Price
patent: 4491860 (1985-01-01), Lim
patent: 4507756 (1985-03-01), McElroy
patent: 4667216 (1987-05-01), Bigall et al.
T. H. Baker, L. E. Freed, C. L. Kaufman & D. Tuman, "Three-Layered Underpass Resistor Structure", vol. 14, No. 10, Mar. 1972, p. 2902.
R. Levi, "Reactive Ion Etch Technique for Reducing Series Resistance in Large-Scale Integrated Devices", vol. 20, No. 8, Jan. 1978, pp. 3127 & 3128.
Sikes William L.
Telefunken electronic GmbH
Wise Robert E.
LandOfFree
Integrated circuit arrangement does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit arrangement, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit arrangement will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-938468