Thin film transistor

Details Thin film transistor Thin film transistor

1991-03-01

1992-06-23

Davie, James W.

357 237, H01L 2978

Patent

active

051247690

ABSTRACT:
The thin film transistor comprises source and drain regions, a channel forming region formed between the source and drain regions, a first (main) gate for turning on or off the transistor, and in particular at least one second (sub-) gate for reducing turn-off leakage current. When the n-channel transistor is turned off, for example, a negative voltage is applied to the main gate to form a p-channel layer in the channel forming region under the main gate and a positive voltage is applied to the subgate to form an n-channel layer in the channel forming region under the subgate, for instance, so that a pn junction can be formed between under the main gate and the subgate to reduce the turn-off leakage current. The above-mentioned disclosure can be clearly applied to p-channel transistors. Further, the above four-terminal transistor can be simply modified to a three-terminal transistor by connecting the main gate to the subgate via a diode or a capacitor or by directly connecting the drain region to the subgate. Further, the above three-terminal transistor can be manufactured in accordance with only the ordinary device manufacturing process.

REFERENCES:
patent: 4065781 (1977-12-01), Gutknecht
patent: 4984040 (1991-01-01), Yap
patent: 4984041 (1991-01-01), Hack et al.
patent: 5012315 (1991-04-01), Shur
patent: 5017983 (1991-05-01), Wu
Proceedings of the IEEE, vol. 55, No. 7, Jul. 1967, N.Y., US, pp. 1217-1218; R. G. Wagner et al., "A Dual Offset Gate Thin-Film Transistor", p. 1218, col. 1, paragraph 2; FIGS. 1, 3b.
Patent Abstracts of Japan, vol. 7, No. 214 (E-199)(1359) Sep. 21, 1983, & JP-A-58 107676 (Nippon Denki K.K.) Jun. 27, 1983.
Patent Abstracts of Japan, vol. 6, No. 218 (E-139)(1096) Nov. 2, 1982, & JP-A-57 121277 (Hitachi Seisakusho K.K.) Jul. 28, 1982.
International Journal of Electronics, vol. 54, No. 2, Feb. 1983, London GB, pp. 287-298; K. V. Anand et al., "A Novel p-n Junction Polycrystalline Silicon Gate MOSFET".
Patent Abstracts of Japan, vol. 10, No. 263 (E-435)(2319) Sep. 9, 1986, & JP-A-61 88565 (Sony Corp.), May 6, 1986.

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