Symmetric vertical MOS transistor with improved high voltage ope

Details Symmetric vertical MOS transistor with improved high voltage ope Symmetric vertical MOS transistor with improved high voltage ope

1991-01-03

1992-06-23

Larkins, William D.

357 238, H01L 2978

Patent

active

051247640

ABSTRACT:
An MOS transistor having a vertical channel disposed along the sides of a trench is disclosed. The transistor is formed in an epitaxial layer on a substrate, with the channel region formed within the epitaxial layer by way of ion implantation and diffusion; the ion implantation is done in such a manner that the epitaxial layer is divided into a portion above the channel region (source region) and a portion below the channel region (drain region). A trench is etched to extend through the epitaxial region into the substrate, gate oxide is grown along the sides of the trench, and a polysilicon gate electrode is deposited adjacent the gate oxide along the walls of the trench. The epitaxial layer allows the drain and source regions of the transistor to have substantially equal carrier concentrations, said concentrations being relatively low. As a result, the transistor operates the same regardless of whether the upper portion of the epitaxial layer serves as the drain or as the source, for digital logic applications. In addition, the relatively light doping of the source and drain regions provides for a high diode breakdown voltage, and prevents punch-through of the channel region at high bias voltages.

REFERENCES:
patent: 3518509 (1970-06-01), Cullis
patent: 3893155 (1975-07-01), Ogiue
patent: 4462040 (1984-07-01), Ho et al.
patent: 4589004 (1986-05-01), Yasuda et al.
patent: 4630088 (1986-12-01), Ogura et al.
patent: 4740826 (1988-04-01), Chatterjee
patent: 5016068 (1991-05-01), Mori
Semiconductor Devices, S. M. Sze, pp. 200-207 (New York, John Wiley and Sons: 1985).

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