Semiconductor integrated circuit capable of synchronous and asyn

Details Semiconductor integrated circuit capable of synchronous and asyn Semiconductor integrated circuit capable of synchronous and asyn

1991-04-25

1992-06-23

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072722, 307475, 307480, 36518905, 371 211, H03K 19092

Patent

active

051245892

ABSTRACT:
A self-timed random-access memory device includes randomly accessible memory circuitry (7), a clock generator (9) responsive to an external clock signal for generating an internal clock signal, an input circuit (8') responsive to the internal clock signal for latching and outputting a supplied input signal, an output circuit (11') responsive to the internal clock signal for latching and outputting an output from the memory device, and circuitry (81, 82, 85, 86; 115, 116, 124, 125; 135, 136, 144, 145) responsive to a through state specifying signal (TH, THM) for disabling the latch function of the input circuit and the output circuit. The memory device can be switched, in response to the through state specifying signal, between a mode operating synchronously with the externally supplied clock signal and another mode operating asynchronously with the externally supplied clock signal.

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patent: 4756006 (1988-07-01), Rickard
patent: 4761567 (1988-08-01), Walters, Jr. et al.
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patent: 4812678 (1989-03-01), Abe
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patent: 4972518 (1990-11-01), Matsuo
patent: 5003204 (1991-03-01), Cushing et al.
patent: 5017813 (1991-05-01), Galbraith et al.

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