Process for fabricating heterojunction bipolar transistors

Details Process for fabricating heterojunction bipolar transistors Process for fabricating heterojunction bipolar transistors

1988-12-20

1991-01-08

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 33, 437192, 437203, 437909, 148DIG10, 148DIG11, 148DIG72, 148DIG100, H01L 21265, H01L 21331, H01L 21441

Patent

active

049835327

ABSTRACT:
Microfabrication and large scale integration of a device can be realized by using a planar heterojunction bipolar transistor formed by a process comprising successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that at least one of the emitter junction and collector junction is a heterojunction, wherein a collector drawing-out metal layer is formed by the selective CVD method.

REFERENCES:
patent: 4641420 (1987-02-01), Lee
patent: 4720908 (1988-01-01), Wills
Tauber et al., Silicon Processing for the VLSI Era, 1986, pp. 400-405.

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